The present invention relates in general to a method and apparatus for bypassing scannable memory devices, such as scannable register arrays, which eliminates the need for external shift register latches and other logic components.
As the packing density of integrated circuit chip devices has increased greatly in recent years, various schemes have been devised for providing increased testability of the devices. One particularly effective testing scheme employs level sensitive scan design (LSSD) in which chains of shift register latches (SRLs) are integrally formed in the device circuit to facilitate testing. The SRLs provide internal control points and observation points in the circuit to permit application of control test inputs to the circuit's various logic devices, and observation of the outputs which result from the inputs. The SRLs form a shift or scan path through which test data can be propagated.
In the operation of an LSSD testing scheme, a serial test data stream is first propagated through the scan path. A control pulse is then applied to the logic circuitry in the device to cause it to operate through one cycle using as input, the data in the SRLs at the various control points. The resulting serial data stream is then propagated out of the scan path to an external buffer where it is analyzed to determine if the digital values at the various observation points indicate that the logic circuitry is functioning properly. This procedure is repeated numerous times to ensure that all logic circuitry is tested.
Although the scan design testing scheme is very effective, the maximum scan path length, and therefore the maximum number of SRLs in the scan path, is limited by time constraints since the test data is propagated serially, and each SRL adds an additional scan cycle delay to the total time required for propagation of the test data through the scan path. Thus, the more SRLs that are added to the scan path, the longer the length of time required for the testing procedures. This becomes more and more of a problem as integrated circuit fabrication technology continues to improve and permit greater and greater packing density.
The current design of many memory device circuits also adds to the foregoing problem. More particularly, many memory devices, such as register arrays, are implemented with memory cells or bits that are each comprised of an LSSD L1/L2 latch, which facilitates connection of the array bits in the LSSD scan path. This permits the register array to be tested in the same manner as the logic circuitry, thereby eliminating the requirement for array test techniques, such as those using Array Built-In Self Test (ABIST), that require additional area for supplying test patterns from the test logic through the surrounding chip logic to the register array. However, the test time, volume of test data required behind each scan input, and number of I/Os that are consumed for scanning become prohibitively large if multiple scannable register arrays are provided on the same circuit chip, since each bit in the arrays forms part of the scan path length. This necessitates that a plurality of scan paths and associated I/O pins be provided on each chip to avoid exceeding a maximum allowable number of SRLs in each scan path. Unfortunately, each additional scan path requires the use of two additional I/O pins for applying and receiving signal data to and from the scan path. This can present a serious problem for I/O constrained designs, especially since the number of economic test function I/Os is limited.
One proposed solution to this specific problem presented by scannable memory devices, such as scannable register arrays, is to employ a bypass scheme wherein the bits of the register arrays can be selectively bypassed during testing to reduce the scan path length substantially. With the bypass scheme, circuit testing is performed in two modes. In the first, bypass mode, all logic surrounding the register arrays is tested using the reduced scan path length. Then, the circuit is placed in the non-bypass mode for the remainder of the test, during which only the register ar rays are tested. The total time required for testing the circuit is thus substantially reduced since the scan path length is substantially shorter during the logic component testing, and only the array bits are tested during the non-bypass mode.
To bypass the register array, extra latches and multiplexors must be inserted to observe upstream logic and control downstream logic. A set of SRLs known as "listening latches" is thus introduced with one latch at each input of the register array. These listening latches are multiplexed with the register array outputs to preserve the observability of upstream logic and controllability of downstream logic during scan-bypass mode. Although this arrangement reduces the test time significantly, the number of listening latches and multiplexors needed by this scheme can be large if the number of inputs to and outputs from the register array is large. This increases the overall chip area necessary to implement the circuit. Also, the multiplexors introduce undesirable additional delay in the functional path from the register array.